In general, a packet relay apparatus is provided with a plurality of interfaces, a switch connecting the interfaces and a control device in charge of controlling the packet relay apparatus. A packet received by a certain interface (an ingress-side interface) is transferred by the switch to an interface (an egress-side interface) corresponding to a destination of the packet and transmitted from the egress-side interface. The interface is provided with buffers (queues) each of which temporarily accumulates packets, a shaper and a scheduler. The shaper has a function of controlling (suppressing) the transmission rate of packets, for example, by adjusting readout intervals of packets to be read from the buffers for each packet flow. The scheduler has a function of determining the order and a readout time of the packets being read from the buffers.
The shaper and the scheduler are roughly categorized as an “output type” or an “input type” according to positions where the shaper and the scheduler are arranged relative to the buffers. In the case of the “output type”, the shaper and the scheduler are arranged at a subsequent stage of the buffers. An arrived packet is once accumulated in a buffer and then read in accordance with shaping and scheduling algorithms. On the other hand, in the “input type”, the shaper and the scheduler are arranged at a previous stage of the buffers. In the case of the “input type”, after a readout time at which an arrived packet is read from a buffer is determined in accordance with the shaping and scheduling algorithms, the arrived packet is accumulated into a buffer corresponding to the readout time. Outputting of packets is performed by reading a cue of packets arranged in order of time, in accordance with readout times.
For more information, see Japanese Laid-open Patent Publication No. 2000-299686 and Japanese Laid-open Patent Publication No. 2004-363901.